1. Field of the Invention
This invention relates to computer technology, and more particularly, to a method of selecting registers.
2. Description of Related Art
FIG. 1 shows a conventional architecture of a primitive register set. As shown, the primitive register set includes six modes: Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5; wherein Mode 0 includes 15 physical registers R0-R14 and one physical program counter PC; Mode 1 includes 13 virtual registers R0-R12, two physical registers R13_SVC, R14_SVC, and one virtual program counter PC; Mode 2 includes 13 virtual registers R0-R12, two physical registers R13_ABORT, R14_ABORT, and one virtual program counter PC; Mode 3 includes 13 virtual registers R0-R12, two physical registers R13_UNDEF, R14_UNDEF, and one virtual program counter PC; Mode 4 includes 13 virtual registers R0-R12, two physical registers R13_IRQ, R14_IRQ, and one virtual program counter PC; Mode 5 includes 8 of virtual registers R0-R7, 7 physical registers R8_FIQ-R14_FIQ, and one virtual program counter PC.
To gain access to one of the registers shown in FIG. 1, it requires the use of 3 bits for mode selection and another 4 bits for register selection. For example, when it is desired to gain access to (Mode 2, R7), it is required to use (010) to select Mode 2 and then use (0111) to select the register R7 in Mode 2. However, since R7 in Mode 2 is a virtual register, the access will be then redirected to the physical register R7 in Mode 0. This operation would result in the use of redundant bits and a slower access speed, making the register access operation quite inefficient.
It is therefore an objective of this invention to provide a new method of selecting registers, which can help reduce the number of access bits and reduce access time by rearranging the physical registers in the same mode.
In accordance with the foregoing and other objectives, the invention proposes a new method of selecting registers.
In one preferred embodiment, the method according to the invention is used for selecting registers from a primitive register set; the primitive register set including six modes of registers, including a Mode 0, a Mode 1, a Mode 2, a Mode 3, a Mode 4, and a Mode 5; wherein the Mode 0 contains 15 physical registers and one physical program counter; the Mode 1 contains 13 virtual registers, two physical registers, and one virtual program counter; the Mode 2 contains 13 virtual registers, two physical registers, and one virtual program counter; the Mode 3 contains 13 virtual registers, two physical registers, and one virtual program counter; the Mode 4 contains 13 virtual registers, two physical registers, and one virtual program counter; and the Mode 5 contains 8 virtual registers, 7 physical registers, and one virtual program counter; and wherein the selection of one of one of the 13 virtual registers and the virtual program counter in the Mode 0, the 13 virtual registers and the virtual program counter in the Mode 1, the 13 virtual registers and the virtual program counter in the Mode 2, the 13 virtual registers and the virtual program counter in the Mode 3, the 13 virtual registers and the virtual program counter in the Mode 4, and the 8 virtual registers and the virtual program counter in the Mode 5 is mapped to one of the 15 physical registers and the one physical program counter in the Mode 0.
The first preferred embodiment of the method according to the invention comprises the step of: (1) mapping the primitive register set to a converted register set; the converted register set including two converted modes of registers, including a Converted Mode 0 and a Converted Mode 1; wherein the Converted Mode 0 contains 15 physical registers and one physical program counter; and the Converted Mode 1 contains 15 physical registers and one virtual program counter; wherein the 15 physical registers in the Converted Mode 0 are mapped to the 15 physical registers in the Mode 0 of the primitive register set; the one physical program counter in the Converted Mode 0 is mapped to the one physical program counter in the Mode 0 of the primitive register set; the 15 physical registers in the Converted Mode 1 are mapped in a predetermined one-to-one correspondence to the 2 physical registers in the Mode 1 of the primitive register set, the 2 physical registers in the Mode 2 of the primitive register set, the 2 physical registers in the Mode 3 of the primitive register set, the 2 physical registers in the Mode 4 of the primitive register set, and the 7 physical registers in the Mode 5 of the primitive register set; the one virtual program counter in the Converted Mode 1 is mapped to one of the 5 virtual program counters respectively in the Mode 1, the Mode 2, the Mode 3, the Mode 4, and the Mode 5 of the primitive register set.
Next, a mode-selection bit is issued, whose value indicates the mode that contains the register to be selected; and then, a register-selection bit sequence is issued, whose value indicates the register to be selected from the selected mode. Based on these selection bits, either the Converted Mode 0 or the Converted Mode 1 is selected based on the value of the mode-selection bit; and then selecting one of the registers in the selected mode indicated by the 4-bit register-selection bit sequence.
In another preferred embodiment, the method according to the invention is used for selecting registers from a primitive register set. The primitive register set includes six modes of registers including a Mode 0, a Mode 1, a Mode 2, a Mode 3, a Mode 4, and a Mode 5; wherein the Mode 0 contains 15 physical registers and one physical program counter; the Mode 1 contains 13 virtual registers, two physical registers, and one virtual program counter; the Mode 2 contains 13 virtual registers, two physical registers, and one virtual program counter; the Mode 3 contains 13 virtual registers, two physical registers, and one virtual program counter, the Mode 4 contains 13 virtual registers, two physical registers, and one virtual program counter; and the Mode 5 contains 8 virtual registers, 7 physical registers, and one virtual program counter; and wherein the selection of one of one of the 13 virtual registers and the virtual program counter in the Mode 0, the 13 virtual registers and the virtual program counter in the Mode 1, the 13 virtual registers and the virtual program counter in the Mode 2, the 13 virtual registers and the virtual program counter in the Mode 3, the 13 virtual registers and the virtual program counter in the Mode 4, and the 8 virtual registers and the virtual program counter in the Mode 5 is mapped to one of the 15 physical registers and the one physical program counter in the Mode 0; and wherein the converted register set includes two converted modes of registers, including a Converted Mode 0 and a Converted Mode 1; wherein the Converted Mode 0 contains 15 physical registers and one physical program counter; and the Converted Mode 1 contains 15 physical registers and one virtual program counter.
The second preferred embodiment of the method according to the invention comprises the steps of: issuing a selection bit sequence which includes a first part for mode selection and a second part for register selection; if the first part of the selection bit sequence selects the Mode 0, converting it for selection of Mode 0, and then the register indicated by the second part of the selection bit sequence is mapped to one of the physical registers and physical program counter in the Converted Mode 0; if the first part of the selection bit sequence selects one of the Mode 1, the Mode 2, the Mode 3, the Mode 4, and the Mode 5, mapping it to the Converted Mode 1; and if the second part of the selection bit sequence selects one of the two physical registers in the Mode 1, the two physical registers in the Mode 2, the two physical registers in the Mode 3, the two physical register in Mode 4, or the 7 physical registers in the Mode 5, mapping it to one of the 15 physical registers in the Converted Mode 1; and if the first part of the selection bit sequence selects one of the Mode 1, the Mode 2, the Mode 3, the Mode 4, the Mode 5, and the second part thereof selects one of the 13 virtual registers and one virtual program counter in Mode 1, or one of the 13 virtual registers and one virtual program counter in Mode 2, or one of the 13 virtual registers and one virtual program counter in Mode 3, or one of the 13 virtual registers and one virtual program counter in Mode 4, or one of the 13 virtual registers and virtual program counter in Mode 5, mapping it to one of the 15 physical registers and one physical program counter in the Converted Mode 0.
Compared to the prior art, since the invention needs just to select between 2 modes from the converted register set, rather than 6 modes from the primitive register set, it needs a reduced number of bits for the selection and allows a reduced access time.